1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor integrated circuits and, more particularly, to the formation of layers of metal interconnection formed after formation of electronic components such as transistors, resistors and capacitors thereon.
2. Description of the Prior Art
Techniques for fabrication of semiconductor integrated circuits have become highly developed in recent years in order to achieve high performance components at increased integration density. It is often the case that components formed at reduced sizes exhibit improved performance in terms of reduced power consumption and increased switching speed. Additionally, high integration density allows increased functionality of the circuitry which can be formed on a single chip and reduced signal propagation time between components. Further, the formation of increased numbers of components on a chip can be done with little increase of process cost. Accordingly, there is substantial incentive toward higher levels of integration density and design rules permitting smaller minimum feature sizes for integrated circuits. Accordingly, techniques of material deposition and patterning must be continually developed to support design rules permitting smaller minimum feature sizes at acceptable levels of manufacturing yield.
To efficiently achieve high integration density, lithography is generally the process of choice to achieve a high degree of repeatability and high manufacturing yield at relatively low cost. However, lithographic exposures are most reliable when a resist is placed on a planar surface while it is the purpose of lithography to form patterns of material having a finite feature thickness in or on the surface at which it is performed. The complex component structures characteristic of modern semiconductor integrated circuits often require dozens or even hundreds of sequential lithographic processes to form and the formation of patterns of material over other patterned material often causes topography of sufficient severity to impose limits on, if not compromise, subsequent lithographic processes. While it is common to deposit a relatively thick layer of material which is later planarized by polishing, there are numerous structures which will not tolerate the mechanical loads imposed by the polishing process or the potential for surface contamination which are unavoidable in the polishing process.
Some structures formed over severe topography may be compromised by the topography even when seemingly formed in accordance with the design. Metal conductors, for example, are particularly vulnerable to metal migration when even slight irregularities are present which may cause localized concentration of current therein since metal migration is principally a current-driven diffusion process. Such concentration of current may also occur where conductors cross other structures and the conductor path abruptly changes direction, especially relative to the plane of the substrate on which the integrated circuit is formed. Unfortunately, as severity of topography increases, these locations of change of direction of the conductor path become more likely to be formed with reduced thickness which increases current density and the potential for metal migration.
Additionally, modern integrated circuits often utilize a metallization layer which is later patterned into conductors as substantially the last layer or last few layers to be deposited. The final metallization layer is often used to form connections to a previously formed conductor layer in order to accommodate needs of connections to cross each other. For example, the connections in the two layers can be linear and oriented orthogonally to each other. For high integration density, connection is often made to previously formed components or connections through apertures, referred to as vias, in insulator or passivation layers. These vias must be formed with high registration accuracy and are often formed at the minimum feature size allowed by the integrated circuit design rules in order to avoid making erroneous connections to or bridging between portions of components or connections.
Registration or position accuracy and size regulation when the vias are formed may be compromised by the severity of the surface topography on which a lithographic exposure must be made in order to form the vias and expose the component portions to which connections are to be made, increasing the need for small feature size of the vias in the lithographic process. Additionally, when the metal layer, in which connections are to patterned, is deposited, the vias themselves constitute severe topography which has been found to present difficulties in the formation of the metal layer. Further, for the final metal layer, similar topography will be caused at the surface of an insulator layer formed over a previously deposited array of conductors.
Ideally, vias are filled with metal during this process. However, the deposition of metal is not ideally conformal and the deposition tends to proceed more rapidly on the surface and near the top of the vias than at the bottom of the vias even when the vias are tapered to the maximum degree that does not consume such amounts of space as would reduce integration density. The differential of deposition rates between the top and bottom of a via becomes more pronounced as the process continues and may close the top of the via before the via can be completely filled. When this occurs, a void will remain in the via which is sometimes referred to as a "key-hole defect" because of its distinctive shape in cross-section. Such voids, of course, represent a severe irregularity in the conductor cross-section which can reduce manufacturing yield or increase the potential for failure after the integrated circuit is placed in service. Such a void is not observable by non-destructive inspection.
Topography of sufficient severity to reduce reliability of connections can occur even when the deposition does not close the top of the via, as is more often the case at locations between conductors of a previous metal layer, alluded to above. In this case, a cavity remains which can trap materials and/or prevent adequate coverage by a protective material, either of which can have other deleterious effects on a conductor. In particular, developers for lithographic resists may attack the metal (e.g. AlCu) by causing corrosion or other effects resulting from alteration of surface chemistry by the developers. In the case of AlCu metallization and some other metals and alloys, the altered surface chemistry of the metal acts as a mask which may reduce effectiveness of a subsequent etch, leaving residual metal deposits. Further, conformality of resist to severe topography may result in incomplete resist development or alteration of the surface chemistry of the metal which may result in similarly inadequate metal removal during the etching to pattern the metal into conductors, particularly between conductors of an underlying layer. Thus, when the metal layer is deposited over severe topography in a highly conformal manner, subsequent patterning may leave residual metal between connections which may form metal to metal shorts (when conductors are bridged intralayer or interlayer) or cause reduction in breakdown voltage between conductors.
Conformality of metal deposition can be controlled over a relatively wide range by the temperature at which deposition is carried out. Generally, low temperature (e.g. 150.degree. C.) results in a high degree of conformality but small grain size. Grain size is a factor in resistance to metal migration and small grain size is generally associated with metal instability and low resistance to metal migration. Further, at low temperatures grain orientation will often be vertical (e.g. substantially perpendicular to the substrate) and will cause surface irregularity (although on a much smaller scale) when the device is cooled from even a lower temperature. The smaller irregularity can cause a so-called "ring defect" in a final metal layer such as titanium nitride (TiN), used to protect underlying AlCu from resist developer and to form an antireflective surface, which may be fractured upon cooling.
Metal deposition at higher temperatures produces larger grain size and a generally more planar surface (improving lithographic patterning but reducing conformality of the deposit and greatly increasing the likelihood that voids and topography of increased severity will be formed. Thus, reduction of conformality by higher temperature metal deposition is associated with reduced yield, particularly from metal-to-metal shorts. Further, at temperatures above about 350.degree. C., at which temperature AlCu expands significantly (also exhibited by other alloys and metals at similar but different temperatures), metal from lower metal connections will extrude into the vias causing damage to both the underlying connections and the via connection.
Scanning electron microscope (SEM) imaging has shown residual metal to occur where cusps develop in the surface of the metal as a result of the topography of the underlying insulator layer deposited over conductors which are generally parallel to each other and of substantial thickness. Since these cusps reach a level at which the lower level connectors are formed and the last metal layer is generally used to form conductors orthogonal thereto, both interlayer and intralayer bridging may easily occur: the former when any defect is present in the lower level oxide (which must also be lithographically patterned to form tapered vias but where the lithographic patterning can be compromised by severe topography) and the latter since residual metal extending orthogonally to the last metal layer conductors will be favored.
In summary, so-called cold deposition is too conformal and increases surface topography while forming grains which are susceptible to metal migration. Deposition at increased temperatures forms voids. Unfortunately, with increasing temperature of deposition, the differential between deposition at the top and bottom of severe topography (about 1.2 microns apart) develops before a reduction in conformality sufficient to reduce cusp formation occurs because of the similar effects of differing deposition mechanisms over severe topography. Therefore, there is a need for a new deposition process which avoids void formation while reducing cusping that forms not only peaks but the valleys therebetween and presents a more nearly planar surface for lithographic patterning and which allows avoidance of residual metal deposits even though topography presented by valleys and tapered vias is similar.